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EL8188
Data Sheet May 29, 2009 FN7467.6
Micropower Single Supply Rail-to-Rail Input-Output Precision Op Amp
The EL8188 is a precision low power, operational amplifier. The device is optimized for single supply operation between 2.4V to 5.5V. This enables operation from one lithium cell or two Ni-Cd batteries. The input range includes both positive and negative rail. The EL8188 draws minimal supply current (55A) while meeting excellent DC-accuracy, noise, and output drive specifications.
Features
* Typical 55A Supply Current * 1mV Max Offset Voltage * Typical 1pA Input Bias Current * 266kHz Gain-bandwidth Product * Single Supply Operation Between 2.4V to 5.5V * Rail-to-rail Input and Output * Ground Sensing * Output Sources and Sinks 26mA Load Current
Ordering Information
PART PART NUMBER MARKING EL8188FIZ-T7* (Note 2) 188Z TEMP RANGE (C) PACKAGE (Pb-Free) PKG. DWG. #
* Pb-free (RoHS compliant)
Applications
* Battery - or Solar-powered Systems * 4mA to 20mA Current Loops * Handheld Consumer Products * Medical Devices
-40 to +125 6 Ld WLCSP W3x2.6C (1.5mmx1.0mm) -40 to +125 6 Ld SOT-23 MDP0038
BBYA Coming Soon EL8188FWZ-T7A* (Note 1) Coming Soon EL8188FWZ-T7* (Note 1) Coming Soon EL8188ISZ (Note 1) Coming Soon EL8188ISZ-T7* (Note 1) Coming Soon EL8188ISZ-T13* (Note 1) NOTES: BBYA
-40 to +125 6 Ld SOT-23
MDP0038
* Thermocouple Amplifiers * Photodiode Pre-amps
8188ISZ
-40 to +125 8 Ld SOIC
MDP0027
* pH Probe Amplifiers
Pinouts
8188ISZ -40 to +125 8 Ld SOIC MDP0027 EL8188 (6 LD SOT-23) TOP VIEW
OUT 1 V- 2 IN+ 3 6 V+ 5 DNC 4 INDNC 1 IN- 2 IN+ 3 V- 4 +
EL8188 (8 LD SO) TOP VIEW
8 DNC 7 V+ 6 OUT 5 DNC
8188ISZ
-40 to +125 8 Ld SOIC
MDP0027
*Please refer to TB347 for details on reel specifications. 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pbfree requirements of IPC/JEDEC J STD-020 2. These Intersil Pb-free WLCSP and BGA packaged products products employ special Pb-free material sets; molding compounds/die attach materials and SnAgCu - e1 solder ball terminals, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free WLCSP and BGA packaged products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
+-
EL8188 (6 LD WLCSP) TOP VIEW
1 2
A
DNC
OUT
B
V+
V-
C
IN-
IN+
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004-2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL8188
Absolute Maximum Ratings (TA = +25C)
Supply Voltage (VS) and Pwr-up Ramp Rate . . . . . . . 5.75V, 1V/s Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V Current into IN+, IN-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V to V+ +0.5V ESD Tolerance Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Thermal Information
Thermal Resistance JA (C/W) 6 Ld SOT Package . . . . . . . . . . . . . . . . . . . . . . . . . 230 6 Ld WLCSP Package . . . . . . . . . . . . . . . . . . . . . . . 130 8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 125 Ambient Operating Temperature Range . . . . . . . . .-40C to +125C Storage Temperature Range . . . . . . . . . . . . . . . . . -65C to +150C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
V+ = 5V, V- = 0V, VCM = 2.5V, VO = 2.5V, TA = +25C unless otherwise specified. Boldface limits apply over the operating temperature range, -40C to +125C DESCRIPTION TEST CONDITIONS SOT-23 MIN (Note 3) -1 -1.5 WLCSP -1.5 3 1.1 -25 -600 1 25 600 2.8 48 0.15 0 80 75 100 5 TYP 0.05 MAX (Note 3) +1 +1.5 +1.5 UNIT mV mV mV V/Mo V/C pA pA VP-P nV/Hz pA/Hz V dB dB 100 dB dB 400 V/mV V/mV 3 130 10 250 350 4.994 4.994 4.750 4.7 4.875 4.9975 mV mV mV V V V V
PARAMETER VOS
Input Offset Voltage
V OS -----------------Time V OS --------------T IB
Long Term Input Offset Voltage Stability Input Offset Drift vs Temperature Input Bias Current (See Figure 20)
eN
Input Noise Voltage Peak-to-Peak Input Noise Voltage Density
f = 0.1Hz to 10Hz fO = 1kHz fO = 1kHz Guaranteed by CMRR test VCM = 0V to 5V
iN CMIR CMRR
Input Noise Current Density Input Voltage Range Common-Mode Rejection Ratio
PSRR
Power Supply Rejection Ratio
VS = 2.4V to 5.5V
80 80
AVOL
Large Signal Voltage Gain
VO = 0.5V to 4.5V, RL = 100k to (V+ + V-)/2 VOL; Output low, RL = 100k to (V+ + V-)/2 VOL; Output low, RL = 1k to (V+ + V-)/2 VOH; Output high, RL = 100k to (V+ + V-)/2 VOH; Output high, RL = 1k to (V+ + V-)/2
100 100
VOUT
Maximum Output Voltage Swing SOT-23
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FN7467.6 May 29, 2009
EL8188
Electrical Specifications
V+ = 5V, V- = 0V, VCM = 2.5V, VO = 2.5V, TA = +25C unless otherwise specified. Boldface limits apply over the operating temperature range, -40C to +125C (Continued) DESCRIPTION Maximum Output Voltage Swing WLCSP TEST CONDITIONS VOL; Output low, RL = 100k to (V+ + V-)/2 VOL; Output low, RL = 1k to (V+ + V-)/2 VOH; Output high, RL = 100k to (V+ + V-)/2 VOH; Output high, RL = 1k to (V+ + V-)/2 SR Slew Rate 4.991 4.750 4.7 0.1 0.07 GBWP IS, ON Gain Bandwidth Product Supply Current, Enabled fO = 100kHz SOT-23 35 30 WLCSP 45 40 ISC+ Short Circuit Output Current RL = 10 to opposite supply 23 18 ISCShort Circuit Output Current RL = 10 to opposite supply 20 15 VS Supply Voltage Guaranteed by PSRR 2.4 2.4 NOTE: 3. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 5.5 5.5 26 31 65 266 55 75 85 85 95 0.15 0.19 0.25 MIN (Note 3) TYP 3 130 MAX (Note 3) 10 250 350 4.997 4.875 UNIT mV mV mV V V V V/s V/s kHz A A A A mA mA mA mA V V
PARAMETER VOUT
3
FN7467.6 May 29, 2009
EL8188 Typical Performance Curves
1 RL 10k VOUT = 0.2VP-P 0 GAIN (dB) GAIN (dB) VS = 1.2 -1 VS = 2.5 -2 VS = 1.0 -3 1k 10k 100k 1M
VS = 2.5V, TA = +25C, Unless Otherwise Specified
80 70 60 50 40 30 20 10 0 -10 -20 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) GAIN = 1 GAIN = 10 GAIN = 5 GAIN = 2 GAIN = 1k RL 10k VOUT = 0.2VP-P GAIN = 500 GAIN = 200 GAIN = 100
FREQUENCY (Hz)
FIGURE 1. UNITY GAIN FREQUENCY RESPONSE at VARIOUS SUPPLY VOLTAGES
FIGURE 2. FREQUENCY RESPONSE at VARIOUS CLOSED LOOP GAINS
60 50 40 30 20 10 0 2.0 INPUT OFFSET VOLTAGE (V)
200 AV = -1 VCM = VDD/2 100
SUPPLY CURRENT (A)
0
-100
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-200 -0.5
0.5
1.5
2.5
3.5
4.5
5.5
SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE (V)
FIGURE 3. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 4. INPUT OFFSET VOLTAGE vs OUTPUT VOLTAGE
NORMALIZED INPUT OFFSET VOLTAGE (V)
250
100 80 60 0 45 PHASE 40 20 GAIN 90 135 180 PHASE SHIFT ()
150 GAIN (dB)
50
-50
-150
0 -20 10
-250 -0.5
0.5
1.5
2.5
3.5
4.5
5.5
100
1k
10k
100k
1M
COMMON-MODE INPUT VOLTAGE (V)
FREQUENCY (Hz)
FIGURE 5. INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE
FIGURE 6. OPEN LOOP GAIN AND PHASE vs FREQUENCY (RL = 1k)
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FN7467.6 May 29, 2009
EL8188 Typical Performance Curves
100 90 80 70 PHASE SHIFT () GAIN (dB) CMRR (dB) 60 50 40 30 20 10 0 -10 10 100 1k 10k 100k 1M GAIN 180 PHASE 135 90
(Continued) VS = 2.5V, TA = +25C, Unless Otherwise Specified (Continued)
10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 10 100 1k 10k 100k 1M VCM = 1VP-P RL = 100k AV = +1
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 7. OPEN LOOP GAIN AND PHASE vs FREQUENCY (RL = 100k)
FIGURE 8. CMRR vs FREQUENCY
VOLTAGE NOISE (V)
PSRR (dB)
-30 -40 -50 -60 -70 -80 -90 -100 10
-PSRR +PSRR
100 VOLTAGE
10
10
1
CURRENT 1
100
1k 10k FREQUENCY (Hz)
100k
1M
1
10
100
1k
10k
0.1 100k
FREQUENCY (Hz)
FIGURE 9. PSRR vs FREQUENCY
FIGURE 10. INPUT VOLTAGE AND CURRENT NOISE vs FREQUENCY
20 VOLTAGE NOISE (500nV/DIV) 15 VOS DRIFT (V) 10 5 0 -5 -10 -15 0 TIME (1s/DIV) 500 1000 TIME (HOURS) 1500 1800
2.8VP-P
FIGURE 11. 0.1Hz TO 10Hz INPUT VOLTAGE NOISE
FIGURE 12. VOS DRIFT (SOT-23 PACKAGE) vs TIME
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FN7467.6 May 29, 2009
CURRENT NOISE (pA/Hz)
VS = 1VP-P RL = 100k -10 AV = +1 -20 0
10
1000
100
EL8188 Typical Performance Curves
75 n = 1500 70 65 CURRENT (mA) 60 55 50 MIN 45 40 35 -40 -20 0 20 40 60 80 100 120 MEDIAN CURRENT (A) MAX 80 75 70 65 60 55 50 45 -40 -20 0 20 40 60 80 100 120 MEDIAN MIN
(Continued) VS = 2.5V, TA = +25C, Unless Otherwise Specified (Continued)
85 n = 5000 MAX
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 13. SOT-23 SUPPLY CURRENT vs TEMPERATURE, VS = 2.5V
FIGURE 14. WLCSP SUPPLY CURRENT vs TEMPERATURE, VS = 2.5V
400 n = 1500 300 200 VOS (V) VOS (V) 100 0 -100 -200 MIN -300 -400 -40 -20 0 20 40 60 80 100 120 MEDIAN MAX
800 600 400 200 0 -200 -400 MIN -600 -800 -40 -20 0 20 40 60 80 100 120 MEDIAN MAX n = 1500
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 15. SOT-23 VOS vs TEMPERATURE, VS = 2.5V
FIGURE 16. SOT-23 VOS vs TEMPERATURE, VS = 1.2V
1500 n = 5000 1000 500 VOS (V) 0 MEDIAN -500 -1000 -1500 -40 MIN VOS (V) MAX
1500 n = 5000 1000 500 0 MEDIAN -500 -1000 -1500 -40 MIN MAX
-20
0
20 40 60 80 TEMPERATURE (C)
100
120
-20
0
20 40 60 80 TEMPERATURE (C)
100
120
FIGURE 17. WLCSP VOS vs TEMPERATURE, VS = 2.5V
FIGURE 18. WLCSP VOS vs TEMPERATURE, VS = 1.2V
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FN7467.6 May 29, 2009
EL8188 Typical Performance Curves
160 140 120 IBIAS + (pA) 100 80 60 40 20 MIN 0 -20 -40 -20 0 20 40 60 80 100 120 MEDIAN MAX IBIAS -(pA) n = 1500
(Continued) VS = 2.5V, TA = +25C, Unless Otherwise Specified (Continued)
250 n = 1500 230 210 190 170 150 130 110 90 70 50 30 10 -10 -40 -20 0
MAX
MEDIAN
MIN 20 40 60 80 100 120
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 19. IBIAS+ vs TEMPERATURE, VS = 2.5V
FIGURE 20. IBIAS- vs TEMPERATURE, VS = 2.5V
130 125 120 115 CMRR (dB) 110 105 100 95 90 85 80 -40 -20 0 20 40 60 MIN MEDIAN PSRR (dB) n = 1500 MAX
130 125 120 115 110 105 100 95 90 100 120 85 -40 -20 0 20 40 60 80 100 120 MIN MEDIAN n = 1500 MAX
80
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 21. CMRR vs TEMPERATURE, V+ = 2.5V, 1.5V
FIGURE 22. PSRR vs TEMPERATURE 1.5V TO 2.5V
4.90 n = 1500 4.89 MAX 4.88 VOUT (V) VOUT (V) 4.87 MEDIAN 4.86 4.85 MIN 4.84 -40 -20 0 20 40 60 80 100 120
4.9984 4.9982 4.9980 4.9978 4.9976 4.9974 4.9972 4.9970 4.9968 4.9966 4.9964 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) TEMPERATURE (C) MIN MEDIAN MAX n = 1500
FIGURE 23. VOUT HIGH vs TEMPERATURE, VS = 2.5V, RL = 1k
FIGURE 24. VOUT HIGH vs TEMPERATURE, VS = 2.5V, RL = 100k
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FN7467.6 May 29, 2009
EL8188 Typical Performance Curves
190 180 170 VOUT (mV) MEDIAN VOUT (mV) 160 150 140 MIN 130 120 110 100 -40 -20 0 20 40 60 80 100 120 n = 1500 MAX
(Continued) VS = 2.5V, TA = +25C, Unless Otherwise Specified (Continued)
5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0 -40 -20 0 20 40 60 80 100 120 MIN MEDIAN n = 1500 MAX
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 25. VOUT LOW vs TEMPERATURE, VS = 2.5V, RL = 1k
FIGURE 26. VOUT LOW vs TEMPERATURE, VS = 2.5V, RL = 100k
510 n = 1500 460 410 AVOL (V/mV) 360 MEDIAN 310 260 210 160 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) MIN MAX
FIGURE 27. AVOL vs TEMPERATURE, RL = 100k, VO = 2V @ VS = 2.5V
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FN7467.6 May 29, 2009
EL8188 Pin Descriptions
8 LD SOIC SOT-23 PIN 6 Ld WLCSP EQUIVALENT PIN NUMBER NUMBER PIN NUMBER PIN NAME CIRCUIT 1, 5 2 3 4 8 6 7 4 3 2 5 1 6 C1 C2 B2 A1 A2 B1 DNC ININ+ VDNC OUT V+ Circuit 2 Circuit 3 Circuit 1 Circuit 1 Circuit 3 DESCRIPTION Do Not Connect; Internal connection - Must be left floating. Amplifier's inverting input Amplifier's non-inverting input Negative power supply Do not connect. Pin must be left floating. Amplifier's output Positive power supply
V+
CAPACITIVELY COUPLED ESD CLAMP
V+ ININ+ VCIRCUIT 1 CIRCUIT 2
V+ OUT V-
VCIRCUIT 3
Application Information
Introduction
The EL8188 is a rail-to-rail input and output (RRIO), micro-power, precision, single supply op amp. This amplifier is designed to operate from single supply (2.4V to 5.5V) or dual supply (1.2V to 2.75V) while drawing only 55A of supply current.The device achieves rail-to-rail input and output operation while eliminating the drawbacks of many conventional RRIO op amps.
swing the output in the positive direction. The EL8188 with a 100k load swings to within 3mV of the supply rails.
Results of Over-Driving the Output
Caution should be used when over-driving the output for long periods of time. Over-driving the output can occur in three ways: 1. The input voltage times the gain of the amplifier exceeds the supply voltage by a large value. 2. The output current required is higher than the output stage can deliver. 3. Operating the device in Slew Rate Limit. These conditions can result in a shift in the Input Offset Voltage (VOS) as much as 1V/hr of exposer under these condition.
Rail-to-Rail Input
The PFET input stage of the EL8188 has an input common-mode voltage range that includes the negative and positive supplies without introducing offset errors or degrading performance like some existing rail-to-rail input op amps. Many rail-to-rail input stages use two differential input pairs: a long-tail PNP (or PFET) and an NPN (or NFET). Severe penalties result from using this topology. As the input signal moves from one supply rail to the other, the op amp switches from one input pair to the other causing changes in input offset voltage and an undesired change in the input offset current's magnitude and polarity. The EL8188 achieves rail-to-rail input performance without sacrificing important precision specifications and without degrading distortion performance. The EL8188's input offset voltage exhibits a smooth behavior throughout the entire common-mode input range.
IN+ and IN- Input Protection
In addition to ESD protection diodes to each supply rail, the EL8188 has additional back-to-back protection diodes across the differential input terminals (see "Circuit 1" diagram on page 8). If the magnitude of the differential input voltage exceeds the diode's VF, then one of these diodes will conduct. For elevated temperatures, the leakage of the protection diodes (Circuit 1 pin description table) increases, resulting in the increase in Ibias as seen in Figures 19 and 20. Usage Implications If the input differential voltage is expected to exceed 0.5V, an external current limiting resistor must be used to ensure the input current never exceeds 5mA. For noninverting unity gain applications the current limiting can be via a series IN+ resistor, or via a feedback resistor of appropriate value. For other gain configurations, the series IN+ resistor is the best choice, unless
Rail-to-Rail Output
A pair of complementary MOSFET devices achieves rail-to-rail output swing. The NMOS sinks current to swing the output in the negative direction, while the PMOS sources current to 9
FN7467.6 May 29, 2009
EL8188
the feedback (RF) and gain setting (RG) resistors are both sufficiently large to limit the input current to 5mA. Large differential input voltages can arise from several sources: 1) During open loop (comparator) operation. The IN+ and INinput voltages don't track. 2) When the amplifier is disabled but an input signal is still present. An RL or RG to GND keeps the IN- at GND, while the varying IN+ signal creates a differential voltage. Mux Amp applications are similar, except that the active channel VOUT determines the voltage on the IN- terminal. 3) When the slew rate of the input pulse is considerably faster than the op amp's slew rate. If the VOUT can't keep up with the IN+ signal, a differential voltage results, and visible distortion occurs on the input and output signals. To avoid this issue, keep the input slew rate below 0.2V/s, or use appropriate current limiting resistors.
Proper Layout Maximizes Precision
To achieve the optimum levels of high input impedance (i.e., low input currents) and low offset voltage, care should be taken in the circuit board layout. The PC board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. When input leakage current is a paramount concern, the use of guard rings around the amplifier inputs will further reduce leakage currents. Figure 28 shows a guard ring example for a unity gain amplifier that uses the low impedance amplifier output at the same voltage as the high impedance input to eliminate surface leakage. The guard ring does not need to be a specific width, but it should form a continuous loop around both inputs. For further reduction of leakage currents, mount components to the PC board using Teflon standoffs.
HIGH IMPEDANCE INPUT IN V+
Output Current Limiting
The EL8188 has no internal current-limiting circuitry. If the output is shorted, it is possible to exceed the "Absolute Maximum Rating" for "operating junction temperature", potentially resulting in the destruction of the device.
Power Dissipation
It is possible to exceed the +150C maximum junction temperature (TJMAX) under certain load and power-supply conditions. It is therefore important to calculate TJMAX for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related as follows:
T JMAX = T MAX + ( JA x PD MAX ) (EQ. 1) FIGURE 28. GUARD RING EXAMPLE FOR UNITY GAIN AMPLIFIER
Typical Applications
V+ + EL8188 V-
+ 3V COAX
GENERAL PURPOSE COMBINATION pH PROBE
where PDMAX is calculated using:
V OUTMAX PD MAX = V S x I SMAX + ( V S - V OUTMAX ) x --------------------------R
L
FIGURE 29. pH PROBE AMPLIFIER (EQ. 2)
where: * TMAX = Maximum ambient temperature * JA = Thermal resistance of the package * PDMAX = Maximum power dissipation of the amplifier * VS = Supply voltage * IMAX = Maximum supply current of the amplifier * VOUTMAX = Maximum output voltage swing of the application * RL = Load resistance
A general-purpose combination pH probe has extremely high output impedance typically in the range of 10G to 12G. Low loss and expensive Teflon cables are often used to connect the pH probe to the meter electronics. Figure 29 details a low-cost alternative solution using the EL8188 and a low-cost coax cable. The EL8188 PMOS high impedance input senses the pH probe output signal and buffers it to drive the coax cable. Its rail-to-rail input nature also eliminates the need for a bias resistor network required by other amplifiers in the same application.
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FN7467.6 May 29, 2009
EL8188
R4 100k R3 R2 K TYPE THERMOCOUPLE 10k 10k V+ + EL8188 V-
410V/C + 5V
R1 100k
FIGURE 30. THERMOCOUPLE AMPLIFIER
Thermocouples are the most popular temperature sensing devices because of their low cost, interchangeability, and ability to measure a wide range of temperatures. In Figure 30, the EL8188 converts the differential thermocouple voltage into single-ended signal with 10X gain. The EL8188's rail-to-rail input characteristic allows the thermocouple to be biased at ground and permits the op amp to operate from a single 5V supply.
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FN7467.6 May 29, 2009
EL8188 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL Au
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L
0.010
4x
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. M 2/07
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FN7467.6 May 29, 2009
EL8188 SOT-23 Package Family
e1 A N 6 4
MDP0038
D
SOT-23 PACKAGE FAMILY MILLIMETERS SYMBOL A A1 SOT23-5 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 5 SOT23-6 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 6 TOLERANCE MAX 0.05 0.15 0.05 0.06 Basic Basic Basic Basic Basic 0.10 Reference Reference Rev. F 2/07 NOTES:
E1 2 3
E
A2 b c
0.20 C
0.15 C D 2X 5 e B b NX 1 2 3 2X 0.20 M C A-B D
D E E1 e e1 L L1 N
0.15 C A-B 2X C D
1
3
A2 SEATING PLANE 0.10 C NX A1
1. Plastic or metal protrusions of 0.25mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only).
(L1)
H
6. SOT23-5 version has no center lead (shown as a dashed line).
A
GAUGE PLANE c L 0x +3 -0
0.25
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FN7467.6 May 29, 2009
EL8188 Wafer Level Chip Scale Package (WLCSP)
E
W3x2.6C
3x2 ARRAY 6 BALL WAFER LEVEL CHIP SCALE PACKAGE SYMBOL A MILLIMETERS 0.51 Min, 0.55 Max 0.225 0.015 0.305 0.013 0.323 0.025 0.955 0.020 0.50 BASIC 1.455 0.020 1.00 BASIC 0.50 BASIC 0.25 BASIC 0.00 BASIC Rev. 3 03/08 NOTES: 1. All dimensions are in millimeters.
D PIN 1 ID TOP VIEW
A1 A2 b D D1 E E1 e
A2
SD SE
A A1 b SIDE VIEW
E1 e SE SD 2
D1
1 b C B A
BOTTOM VIEW
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 14
FN7467.6 May 29, 2009

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